74LVC2G74 Datasheet PDF - NXP Semiconductors Single D-type flip-flop Specs

74LVC2G74 - Single D-type flip-flop

Datasheet Summary

Description

The 74LVC2G74 is a single positive-edge triggered D-type ﬂip-ﬂop with individual data (D) inputs, clock (CP) inputs, set (SD) and reset (RD) inputs, and complementary Q and Q outputs.

This device is fully speciﬁed for partial power-down applications using IOFF.

Features

I I I I Wide supply voltage range from 1.65 V to 5.5 V 5 V tolerant inputs for interfacing with 5 V logic High noise immunity Complies with JEDEC standard: N JESD8-7 (1.65 V to 1.95 V) N JESD8-5 (2.3 V to 2.7 V) N JESD8-B/JESD36 (2.7 V to 3.6 V) ±24 mA output drive (VCC = 3.0 V) ESD protection: N HBM JESD22-A114F exceeds 2000 V N MM JESD22-A115-A exceeds 200 V CMOS low power consumption Latch-up performance exceeds 250 mA Direct interface with TTL levels Inputs accept voltages up to 5 V Multiple.

Datasheet Details

Part number	74LVC2G74
Manufacturer	NXP Semiconductors
File Size	153.62 KB
Description	Single D-type flip-flop
Datasheet	74LVC2G74 Datasheet
Additional preview pages of the 74LVC2G74 datasheet.

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Full PDF Text Transcription

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74LVC2G74 Rev. 06 — 23 December 2009 www.DataSheet4U.com Single D-type ﬂip-ﬂop with set and reset; positive edge trigger Product data sheet 1. General description The 74LVC2G74 is a single positive-edge triggered D-type ﬂip-ﬂop with individual data (D) inputs, clock (CP) inputs, set (SD) and reset (RD) inputs, and complementary Q and Q outputs. This device is fully speciﬁed for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing damaging backﬂow current through the device when it is powered down. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse.

Published: Jun 8, 2010 |