P89LPC954 Datasheet | NXP Semiconductors

P89LPC952/954 8-bit microcontroller with accelerated two-clock 80C51 core 8 k B/16 k B 3 V byte-erasable flash with 10-bit ADC Rev. 04 - 24 July 2008 Product data sheet 1. General description The P89LPC952/954 is a single-chip microcontroller, available in low cost packages, based on a high performance processor architecture that executes instructions in two to four clocks, six times the rate of standard 80C51 devices. Many system-level functions have been incorporated into the P89LPC952/954 in order to reduce ponent count, board space, and system cost. 2. Features 2.1 Principal Features I 8 k B/16 k B byte-erasable flash code memory organized into 1 k B sectors and 64-byte pages. Single-byte erasing allows any byte(s) to be used as non-volatile data storage. I 256-byte RAM data memory and a 256-byte auxiliary on-chip RAM. I 8-input multiplexed 10-bit ADC with window parator that can generate an interrupt for in or out of range results. Two analog parators with selectable inputs and reference source. I Two 16-bit counter/timers (each may be configured to toggle a port output upon timer overflow or to bee a PWM output) and a 23-bit system timer that can also be used as a RTC. I Two enhanced UARTs with a fractional baud rate generator, break detect, framing error detection, and automatic address detection; 400 k Hz byte-wide I2C-bus munication port and SPI munication port. I High-accuracy internal RC oscillator option, with clock doubler option, allows operation without external oscillator ponents. The RC oscillator option is selectable and fine tunable. Fast switching between the internal RC oscillator and any oscillator source provides optimal support of minimal power active mode with fast switching to maximum performance. I 2.4 V to 3.6 V VDD operating range. I/O pins are 5 V tolerant (may be pulled up or driven to 5.5 V). I 44-pin and 48-pin packages with 40 and 42 I/O pins minimum while using on-chip oscillator and reset options. I Port 5 has high...