PCA9521 Datasheet | NXP Semiconductors

description The PCA9521 is a monolithic bipolar integrated circuit for bus buffering in applications including I2C-bus, SMBus, PMBus, and other systems based on similar principles. The buffer extends the bus load limit by buffering both the SCL and SDA lines. It supports up to 400 p F loads on each side of the buffer at 400 k Hz. Higher capacitance is supported at lower speeds, and lower capacitance at higher speeds up to 1 MHz. The enable function allows sections of the bus to be isolated. Individual parts of the system can be brought on-line successively. This means a controlled start-up using a diverse range of ponents, operating speeds and loads is easily achieved. Systems employing removable ponents on a back-plane (for example, telemunications racks) can use the enable pin and the high-impedance ports on power-down to safely install and remove ponents in active systems. Bus level translation between a very wide range of bus voltages, from 1.8 V to 10 V, is supported. This feature provides enormous flexibility in interfacing systems of different technologies. The unique operation of the PCA9521 provides one of the fastest response times of such bidirectional buffers, ensuring any glitches (mon to other buffers) are kept well within the 50 ns I2C-bus specification. Additionally, it does this without the need for ‘rise-time accelerators’ which, bined with low noise margins, may cause glitches outside of the I2C-bus specification. 2. Features and benefits - Dual, bidirectional unity gain buffer - Fast switching times allow operation in excess of 1 MHz - Supports I2C-bus (Standard-mode and Fast-mode), SMBus (standard and high power mode), PMBus and IPMB - Enable allows bus segments to be disconnected - Low standby current when not enabled - Application/removal of power to IC will not interfere with other bus activity - 6 m A (static) pull-down capability supports a wide range of bus standards - Low noise susceptibility - Low input-output offset voltage - Threshold...