PCKEL14 Datasheet PDF - NXP Semiconductors 2.5 V/3.3 V PECL/ECL 1:5 clock distribution chip Specs

PCKEL14 - 2.5 V/3.3 V PECL/ECL 1:5 clock distribution chip

Datasheet Summary

Description

The PCKEL14 is a low skew 1:5 clock distribution chip designed explicitly for low skew clock distribution applications.

The device can be driven by either a differential or single-ended ECL, or if positive power supplies are used, PECL input signal.

Features

a multiplexed clock input to allow for the distribution of a lower speed scan or test clock along with the high speed system clock. When LOW (or left open and pulled LOW by the input pull-down resistor), the SEL pin will select the differential clock input. The common enable (EN) is synchronous, so that the outputs will only be enabled/disabled when they are already in the LOW state. This avoids any chance of generating a runt clock pulse when the device is enabled/disabled, as can happen with a.

Datasheet Details

Part number	PCKEL14
Manufacturer	NXP Semiconductors
File Size	428.56 KB
Description	2.5 V/3.3 V PECL/ECL 1:5 clock distribution chip
Datasheet	PCKEL14 Datasheet
Additional preview pages of the PCKEL14 datasheet.

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Full PDF Text Transcription

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www.DataSheet.co.kr PCKEL14 2.5 V/3.3 V PECL/ECL 1:5 clock distribution chip Rev. 01 — 14 October 2002 Product data 1. Description The PCKEL14 is a low skew 1:5 clock distribution chip designed explicitly for low skew clock distribution applications. The device can be driven by either a differential or single-ended ECL, or if positive power supplies are used, PECL input signal. The PCKEL14 is designed to operate in ECL or PECL mode for a voltage supply range of −2.375 V to −3.8 V (or 2.375 V to 3.8 V). The PCKEL14 features a multiplexed clock input to allow for the distribution of a lower speed scan or test clock along with the high speed system clock. When LOW (or left open and pulled LOW by the input pull-down resistor), the SEL pin will select the differential clock input.

Published: Oct 20, 2011 |