PX1012A Datasheet PDF - NXP Semiconductors PCI Express stand-alone X1 PHY Specs

PX1012A - PCI Express stand-alone X1 PHY

This page provides the datasheet information for the PX1012A, a member of the PX1011A PCI Express stand-alone X1 PHY family.

Datasheet Summary

Description

The PX1011A/PX1012A is a high-performance, low-power, single-lane PCI Express electrical PHYsical layer (PHY) that handles the low level PCI Express protocol and signaling.

The PX1011A/1012A PCI Express PHY is compliant to the PCI Express Base Speciﬁcation, Rev.

1.0a, and Rev.

Features

such as clock and data recovery (CDR), data serialization and de-serialization, 8b/10b encoding, analog buffers, elastic buffer and receiver detection, and provides superior performance to the Media Access Control (MAC) layer devices. The PX1011A/1012A is a 2.5 Gbit/s PCI Express PHY with 8-bit data PXPIPE interface. Its PXPIPE interface is a superset of the PHY Interface for the PCI Express (PIPE) speciﬁcation, enhanced and adapted for off-chip.

Datasheet Details

Part number	PX1012A
Manufacturer	NXP Semiconductors
File Size	276.03 KB
Description	PCI Express stand-alone X1 PHY
Datasheet	PX1012A Datasheet
Additional preview pages of the PX1012A datasheet.

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Full PDF Text Transcription

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PX1011A/PX1012A PCI Express stand-alone X1 PHY Rev. 02 — 18 May 2006 Product data sheet 1. General description The PX1011A/PX1012A is a high-performance, low-power, single-lane PCI Express electrical PHYsical layer (PHY) that handles the low level PCI Express protocol and signaling. The PX1011A/1012A PCI Express PHY is compliant to the PCI Express Base Speciﬁcation, Rev. 1.0a, and Rev. 1.1. The PX1011A/1012A includes features such as clock and data recovery (CDR), data serialization and de-serialization, 8b/10b encoding, analog buffers, elastic buffer and receiver detection, and provides superior performance to the Media Access Control (MAC) layer devices. The PX1011A/1012A is a 2.5 Gbit/s PCI Express PHY with 8-bit data PXPIPE interface.

Published: May 13, 2011 |