74ABT823 Description
The 74ABT823 Bus interface Register is designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data/address paths of buses carrying parity. The 74ABT823 is a 9-bit wide buffered register with Clock Enable (CE) and Master Reset (MR) which are ideal for parity bus interfacing in high microprogrammed systems. The register is fully edge-triggered.
74ABT823 Key Features
- High speed parallel registers with positive edge-triggered D-type
- Ideal where high speed, light loading, or increased fan-in are
- Output capability: +64mA/-32mA
- Latch-up protection exceeds 500mA per Jedec Std 17
- ESD protection exceeds 2000 V per MIL STD 883 Method 3015
- Power-up 3-State
- Power-up Reset