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74ALS109A - Dual J-K positive edge-triggered flip-flop

General Description

The 74ALS109A is a dual positive edge-triggered JK-type flip-flop featuring individual J, K, clock, set, and reset inputs; also true and complementary outputs.

Set (SD) and reset (RD) are asynchronous active-Low inputs and operate independently of the clock (CP) input.

Key Features

  • without notice, in the products, including circuits, standard cells, and/or.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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INTEGRATED CIRCUITS 74ALS109A Dual J-K positive edge-triggered flip-flop with set and reset Product specification IC05 Data Handbook 1991 Feb 08 Philips Semiconductors Philips Semiconductors Product specification Dual J-K positive edge triggered flip-flop with set and reset 74ALS109A DESCRIPTION The 74ALS109A is a dual positive edge-triggered JK-type flip-flop featuring individual J, K, clock, set, and reset inputs; also true and complementary outputs. Set (SD) and reset (RD) are asynchronous active-Low inputs and operate independently of the clock (CP) input. The J and K are edge-triggered inputs which control the state changes of the flip-flops as described in the function table.