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74ALS112A - Dual J-K negative edge-triggered flip-flop

General Description

The 74ALS112A, dual negative edge-triggered JK-type flip-flop

Key Features

  • individual J, K, clock (CPn), set (SD), and reset (RD) inputs, true (Qn) and complementary (Qn) outputs. The SD and RD inputs, when Low, set or reset the outputs as shown in the function table regardless of the level at the other inputs. A High level on the clock (CPn) input enables the J and K inputs and data will be accepted. The logic levels at the J and K inputs may be allowed to change while the CPn is High and the flip-flop will perform according to the function table as long as minimum se.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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INTEGRATED CIRCUITS 74ALS112A Dual J-K negative edge-triggered flip-flop Product specification IC05 Data Handbook 1996 June 27 Philips Semiconductors Philips Semiconductors Product specification Dual J-K negative edge-triggered flip-flop 74ALS112A DESCRIPTION The 74ALS112A, dual negative edge-triggered JK-type flip-flop features individual J, K, clock (CPn), set (SD), and reset (RD) inputs, true (Qn) and complementary (Qn) outputs. The SD and RD inputs, when Low, set or reset the outputs as shown in the function table regardless of the level at the other inputs. A High level on the clock (CPn) input enables the J and K inputs and data will be accepted.