74ALS112A Datasheet | NXP Semiconductors

DESCRIPTION The 74ALS112A, dual negative edge-triggered JK-type flip-flop features individual J, K, clock (CPn), set (SD), and reset (RD) inputs, true (Qn) and plementary (Qn) outputs. The SD and RD inputs, when Low, set or reset the outputs as shown in the function table regardless of the level at the other inputs. A High level on the clock (CPn) input enables the J and K inputs and data will be accepted. The logic levels at the J and K inputs may be allowed to change while the CPn is High and the flip-flop will perform according to the function table as long as minimum setup and hold times are observed. Output changes are initiated by the High-to-Low transition of the CPn. TYPICAL SUPPLY CURRENT (TOTAL) 3.0m A PIN CONFIGURATION CP0 K0 J0 SD0 Q0 Q0 Q1 GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC RD0 RD1 CP1 K1 J1 SD1 Q1 SF00103 TYPE 74ALS112A TYPICAL f MAX 50MHz ORDERING INFORMATION ORDER CODE DESCRIPTION MERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C 74ALS112AN 74ALS112AD DRAWING NUMBER 16-pin plastic DIP 16-pin plastic SO SOT38-4 SOT109-1 INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS CP0, CP1 J0, J1 K0, K1 SD0, SD1 RD0, RD1 Q0, Q1, Q0, Q1 DESCRIPTION Clock Pulse input (active falling edge) J inputs K inputs Set inputs (active-Low) Reset inputs (active-Low) Data outputs 74ALS (U.L.) HIGH/LOW 1.0/1.0 1.0/2.0 1.0/2.0 1.0/2.0 1.0/2.0 20/80 LOAD VALUE HIGH/LOW 20µA/0.1m A 20µA/0.2m A 20µA/0.2m A 20µA/0.2m A 20µA/0.2m A 0.4m A/8m A NOTE: One (1.0) ALS unit load is defined as: 20µA in the High state and 0.1m A in the Low state. LOGIC SYMBOL 3 11 2 12 IEC/IEEE SYMBOL 3 1 1 4 15 13 10 14 J0 CP0 SD0 RD0 CP1 SD1 RD1 Q0 Q0 Q1 Q1 11 13 12 14 10 VCC = Pin 16 GND = Pin 8 5 6 9 7 J1 K0 K1 2 15 4 1J C1 1K R S 2J C2 2K R S 7 9 SF00104 SF00105 1996 Jun 27 853-1846 16995 Philips Semiconductors Product specification Dual J-K negative edge-triggered flip-flop LOGIC DIAGRAM 5, 9 Qn 6, 7 Qn 4, 10 SDn 2, 12 Kn 15, 14 RDn 3, 11 Jn VCC = Pin 16...