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74ALS112A - Dual J-K negative edge-triggered flip-flop

Datasheet Summary

Description

The 74ALS112A, dual negative edge-triggered JK-type flip-flop

Features

  • individual J, K, clock (CPn), set (SD), and reset (RD) inputs, true (Qn) and complementary (Qn) outputs. The SD and RD inputs, when Low, set or reset the outputs as shown in the function table regardless of the level at the other inputs. A High level on the clock (CPn) input enables the J and K inputs and data will be accepted. The logic levels at the J and K inputs may be allowed to change while the CPn is High and the flip-flop will perform according to the function table as long as minimum se.

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Datasheet Details

Part number 74ALS112A
Manufacturer NXP
File Size 92.64 KB
Description Dual J-K negative edge-triggered flip-flop
Datasheet download datasheet 74ALS112A Datasheet
Additional preview pages of the 74ALS112A datasheet.

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Full PDF Text Transcription

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INTEGRATED CIRCUITS 74ALS112A Dual J-K negative edge-triggered flip-flop Product specification IC05 Data Handbook 1996 June 27 Philips Semiconductors Philips Semiconductors Product specification Dual J-K negative edge-triggered flip-flop 74ALS112A DESCRIPTION The 74ALS112A, dual negative edge-triggered JK-type flip-flop features individual J, K, clock (CPn), set (SD), and reset (RD) inputs, true (Qn) and complementary (Qn) outputs. The SD and RD inputs, when Low, set or reset the outputs as shown in the function table regardless of the level at the other inputs. A High level on the clock (CPn) input enables the J and K inputs and data will be accepted.
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