NXP Semiconductors 74ALVC74
The 74ALVC74 is a dual positive-edge triggered, D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs and complementary Q and Q outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. The D inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation.| Part No. | 74ALVC74 |
|---|---|
| Datasheet | 74ALVC74 Download |
| Manufacturer |  NXP Semiconductors |
| Description | Dual D-type flip-flop |
| Buy | Stock & Price |
FEATURES
● Wide supply voltage range from 1.65 to 3.6 V● Complies with JEDEC standard: JESD8-7 (1.65 to 1.95 V) JESD8-5 (2.3 to 2.7 V) JESD8B/JESD36 (2.7 to 3.6 V).
● 3.6 V tolerant inputs/outputs
● CMOS low power consumption
● Direct interface with TTL levels (2.7 to 3.6 V)
● Power-down mode
● Latch-up performance exceeds 250 mA
● ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C. SYMBOL tPHL/tPLH PARAMETER propagation delay nCP to nQ, nQ CONDITIONS VCC = 1.8 V; CL = 30 pF; RL = 1 kΩ VCC = 2.5 V; CL = 30 pF; RL = 500 Ω VCC = 2.7 V; CL = 50 pF; RL = 500 Ω VCC = 3.3 V; CL = 50 pF; RL = 500 Ω tPHL/tPLH propagation delay nSD, nRD to nQ, nQ VCC = 1.8 V; CL = 30 pF; RL = 1 kΩ VCC = 2.5 V; CL = 30 pF; RL = 500 Ω VCC = 2.7 V; CL = 50 pF; RL = 500 Ω VCC = 3.3 V; CL = 50 pF; RL = 500 Ω fmax CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2...
