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74ALVC74PW Datasheet Dual D-type flip-flop

Manufacturer: Nexperia

Overview: 74ALVC74 Dual D-type flip-flop with set and reset; positive-edge trigger Rev. 6 — 27 July 2021 Product data sheet 1.

Download the 74ALVC74PW datasheet PDF. This datasheet also includes the 74ALVC74 variant, as both parts are published together in a single manufacturer document.

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General Description

The 74ALVC74 is a dual positive edge triggered, D-type flip-flop.

It has individual data (nD) inputs, clock (nCP) inputs, set (nSD) and (nRD) inputs, and complementary nQ and nQ outputs.

The set and reset are asynchronous active LOW inputs that operate independently of the clock input.

Key Features

  • Wide supply voltage range from 1.65 V to 3.6 V.
  • Complies with JEDEC standard:.
  • JESD8-7 (1.65 to 1.95 V).
  • JESD8-5 (2.3 to 2.7 V).
  • JESD8B (2.7 to 3.6 V).
  • 3.6 V tolerant inputs/outputs.
  • CMOS low power consumption.
  • Direct interface with TTL levels (2.7 V to 3.6 V).
  • Power-down mode.
  • Latch-up performance exceeds 250 mA.
  • ESD protection:.
  • HBM JESD22-A114E exceeds 2000 V.
  • MM JESD22-A115-A.

📁 Similar Datasheet

Brand Logo Part Number Description Manufacturer
NXP Logo 74ALVC74 Dual D-type flip-flop NXP

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