74ALVCH16646 Overview
The 74ALVCH16646 consists of 16 non-inverting bus transceiver circuits with 3-State outputs, D-type flip-flops and control circuitry arranged for multiplexed transmission of data directly from the internal registers. Data on the ‘A’ or ‘B’ bus will be clocked in the internal registers, as the appropriate clock (CPAB or CPBA) goes to a HIGH logic level. Output enable (OE) and direction (DIR) inputs are provided to...
74ALVCH16646 Key Features
- plies with JEDEC standard no. 8-1A
- CMOS low power consumption
- MULTIBYTETM flow-through pin-out architecture
- Low inductance, multiple VCC and ground pins for minimum noise
