74ALVCH16646DGG Overview
The 74ALVCH16646 consists of 16 non-inverting bus transceiver circuits with 3-state outputs, D-type flip-flops and control circuitry arranged for multiplexed transmission of data directly from the internal registers. Data on the ‘A’ or ‘B’ bus will be clocked in the internal registers, as the appropriate clock (nCPAB or nCPBA) goes to a HIGH logic level. Output enable (nOE) and direction (nDIR) inputs are provided...
74ALVCH16646DGG Key Features
- Wide supply voltage range of 2.3 V to 3.6 V
- CMOS low power consumption
- Direct interface with TTL levels
- Current drive ±24 mA at VCC = 3.0 V
- MULTIBYTE flow-through standard pin-out architecture
- Low inductance multiple VCC and GND pins for minimize noise and ground bounce
- All data inputs have bushold
- Output drive capability 50 Ω transmission lines at 85 °C
- plies with JEDEC standards
- JESD8-5 (2.3 V to 2.7 V)
