NXP Semiconductors 74ALVT16821
The 74ALVT16821 high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive. It is designed for VCC operation at 2.5V or 3.3V with I/O compatibility to 5V. The 74ALVT16821 has two 10-bit, edge triggered registers, with each register coupled to a 3-State output buffer.| Part No. | 74ALVT16821 |
|---|---|
| Datasheet | 74ALVT16821 Download |
| Manufacturer |  NXP Semiconductors |
| Description | 20-bit bus-interface D-type flip-flop |
| Buy | Stock & Price |
FEATURES
● 20-bit positive-edge triggered register● 5V I/O Compatible
● Multiple VCC and GND pins minimize switching noise
● Live insertion/extraction permitted
● Power-up reset
● Power-up 3-State
● Output capability: +64mA/-32mA
● Latch-up protection exceeds 500mA per Jedec Std 17
● ESD protection exceeds 2000V per MIL STD 883 Method 3015 and 200V per Machine Model
DESCRIPTION
The two sections of each register are controlled independently by the clock (nCP) and Output Enable (nOE) control gates. Each register is fully edge triggered. The state of each D input, one set-up time before the Low-to-High clock transition, is transferred to the corresponding flip-flop’s Q output. The 3-State output buffers are designed to drive heavily loaded 3-State buses, MOS memories, or MOS microprocessors. The active Low Output Enable (nOE) controls all ten 3-State buffers independent of the register operation. When nOE is Low, the data in the register appears at the outputs. When nOE is High, the outputs are in high impedance “off” state, which means they will neither drive nor load the bus.
