74ALVT16823 Description
The 74ALVT16823 18-bit bus interface register is designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data/address paths of buses carrying parity. The 74ALVT16823 has two 9-bit wide buffered registers with Clock Enable (nCE) and Master Reset (nMR) which are ideal for parity bus interfacing in high microprogrammed systems. The registers are fully...
74ALVT16823 Key Features
- Two sets of high speed parallel registers with positive
- 5V I/O patible
- Ideal where high speed, light loading, or increased fan-in are
- Live insertion/extraction permitted
- Power-up 3-State
- Power-up Reset
- No bus current loading when output is tied to 5 V bus
- Output capability: +64mA/-32mA
- Latch-up protection exceeds 500mA per Jedec Std 17
- ESD protection exceeds 2000 V per MIL STD 883 Method 3015