| Part Number | 74ALVT16823 Datasheet |
|---|---|
| Manufacturer | Nexperia |
| Overview | The 74ALVT16823 is an 18-bit positive-edge triggered D-type flip-flop with 3-state outputs, reset and enable. The device can be used as two 9-bit flip-flops or one 18-bit flip-flop. The device feature. clock (nCP), clock enable (nCE), master reset (nMR) and output enable (nOE, inputs each controlling 9-bits. When nCE is LOW, the flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (nCP) transition. A HIGH on nOE cause. |
74ALVT16823 Datasheet and Specifications PDF
The 74ALVT16823 is a 18-bit bus-interface D-type flip-flop.
Key Specifications
| Package | SSOP |
|---|---|
| Mount Type | Surface Mount |
| Pins | 56 |
| Operating Voltage | 2.5 V |
| Max Voltage (typical range) | 2.7 V |
| Min Voltage (typical range) | 2.3 V |
| Logic Function | D-Type, Flip-Flop |
| Clock Edge Trigger | Positive Edge |
| Part Number | 74ALVT16823 Datasheet |
|---|---|
| Description | 18-bit bus-interface D-type flip-flop |
| Manufacturer | NXP Semiconductors |
| Overview |
The 74ALVT16823 18-bit bus interface register is designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data/address paths of buses carry.
* Two sets of high speed parallel registers with positive edge-triggered D-type flip-flops DESCRIPTION The 74ALVT16823 18-bit bus interface register is designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data/address paths of buses . |