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74AUP1G14 - Low-power Schmitt-trigger inverter

General Description

The 74AUP1G14 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families.

This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.

Key Features

  • s Wide supply voltage range from 0.8 V to 3.6 V s High noise immunity s ESD protection: x HBM JESD22-A114-C exceeds 2000 V x MM JESD22-A115-A exceeds 200 V x CDM JESD22-C101-C exceeds 1000 V s Low static power consumption; ICC = 0.9 µA (maximum) s Latch-up performance exceeds 100 mA per JESD 78 Class II s Inputs accept voltages up to 3.6 V s Low noise overshoot and undershoot < 10 % of VCC s IOFF circuitry provides partial Power-down mode operation s Multiple package options s Specified from.

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Other Datasheets by NXP Semiconductors

Part Number Description
74AUP1G11 Low-power 3-input AND gate
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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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www.DataSheet4U.com 74AUP1G14 Low-power Schmitt-trigger inverter Rev. 01 — 20 July 2005 Product data sheet 1. General description The 74AUP1G14 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial Power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. The 74AUP1G14 provides a single inverting Schmitt-trigger which accepts standard input signals. It is capable of transforming slowly changing input signals into sharply defined, jitter-free output signals.