74AUP1G175 - Low Power D-Type Flip-Flop

Product Overview

NXP

Part number	74AUP1G175
Manufacturer	NXP
File Size	146.94 KB
Description	Low Power D-Type Flip-Flop
Datasheet	74AUP1G175 Datasheet
Additional preview pages of the 74AUP1G175 datasheet.

The 74AUP1G175 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families.

Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.

s Wide supply voltage range from 0.8 V to 3.6 V s High noise immunity s Complies with JEDEC standards: x JESD8-12 (0.8 V to 1.3 V) x JESD8-11 (0.9 V to 1.65 V) x JESD8-7 (1.2 V to 1.95 V) x JESD8-5 (1.8 V to 2.7 V) x JESD8-B (2.7 V to 3.6 V) s ESD protection: x HBM JESD22-A114-D Class 3A exceeds 5000 V x MM JESD22-A115-A exceeds 200 V x CDM JESD22-C101-C exceeds 1000 V s Low static power consumption; ICC = 0.9 µA (maximum) s Latch-up performance exceeds 100 mA per JESD 78 Class II s Inputs accep.

📁 Similar Datasheet

Other Datasheets by NXP

Published: Dec 14, 2006 |