NXP Semiconductors 74F174
The 74F174 has six edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The register is fully edge-triggered.| Part No. | 74F174 |
|---|---|
| Datasheet | 74F174 Download |
| Manufacturer |  NXP Semiconductors |
| Description | Hex D flip-flops |
| Buy | Stock & Price |
FEATURES
● Six edge-triggered D-type flip-flops● Buffered common Clock
● Buffered, asynchronous Master Reset
DESCRIPTION
The register is fully edge-triggered. The state of each D input, one setup time before the Low-to-High clock transition is transferred to the corresponding flip-flop’s Q output. All Q outputs will be forced Low independent of Clock or Data inputs by a Low voltage level on the MR input. The device is useful for applications where true outputs only are required, and the Clock and Master Reset are common to all storage elements. TYPICAL SUPPLY CURRENT (TOTAL) 35mA PIN CONFIGURATION MR Q0 D0 D1 Q1 D2 Q2 GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC Q5 D5 D4 Q4 D3 Q3 CP SF00188 ORDERING INFORMATIONDESCRIPTION
16-pin plastic DIP 16-pin plastic SO COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C N74F174N N74F174D PKG DWG # SOT38-4 SOT109-1 TYPE 74F174 TYPICAL fMAX 100MHz INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS D0–D5 CP MR Q0–Q5 Data inputs Clock Pulse input (a...
