74F174 Datasheet | NXP Semiconductors

FEATURES - Six edge-triggered D-type flip-flops - Buffered mon Clock - Buffered, asynchronous Master Reset DESCRIPTION The 74F174 has six edge-triggered D-type flip-flops with individual D inputs and Q outputs. The mon buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The register is fully edge-triggered. The state of each D input, one setup time before the Low-to-High clock transition is transferred to the corresponding flip-flop’s Q output. All Q outputs will be forced Low independent of Clock or Data inputs by a Low voltage level on the MR input. The device is useful for applications where true outputs only are required, and the Clock and Master Reset are mon to all storage elements. TYPICAL SUPPLY CURRENT (TOTAL) 35m A PIN CONFIGURATION MR Q0 D0 D1 Q1 D2 Q2 GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC Q5 D5 D4 Q4 D3 Q3 CP SF00188 ORDERING INFORMATION DESCRIPTION 16-pin plastic DIP 16-pin plastic SO MERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C N74F174N N74F174D PKG DWG # SOT38-4 SOT109-1 TYPE 74F174 TYPICAL f MAX 100MHz INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS D0- D5 CP MR Q0- Q5 Data inputs Clock Pulse input (active rising edge) Master Reset input (active-Low) Outputs DESCRIPTION 74F (U.L.) HIGH/LOW 1.0/1.0 1.0/1.0 1.0/1.0 50/33 LOAD VALUE HIGH/LOW 20µA/0.6m A 20µA/0.6m A 20µA/0.6m A 1.0m A/20m A NOTE: One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6m A in the Low state. LOGIC SYMBOL 3 4 6 11 13 14 IEC/IEEE SYMBOL 9 1 C1 R D0 9 1 CP MR D1 D2 D3 D4 D5 3 4 6 1D 2 5 7 10 12 15 Q0 Q1 Q2 Q3 Q4 Q5 11 13 2 VCC = Pin 16 GND = Pin...