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74HC138 - 3-to-8 line decoder/demultiplexer

General Description

The 74HC138; 74HCT138 decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7).

Key Features

  • Complies with JEDEC standard no. 7A.
  • Input levels:.
  • For 74HC138: CMOS level.
  • For 74HCT138: TTL level.
  • Demultiplexing capability.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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74HC138; 74HCT138 3-to-8 line decoder/demultiplexer; inverting Rev. 6 — 28 December 2015 Product data sheet 1. General description The 74HC138; 74HCT138 decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7). The device features three enable inputs (E1, E2 and E3). Every output will be HIGH unless E1 and E2 are LOW and E3 is HIGH. This multiple enable function allows easy parallel expansion to a 1-of-32 (5 to 32 lines) decoder with just four ‘138’ ICs and one inverter. The ‘138’ can be used as an eight output demultiplexer by using one of the active LOW enable inputs as the data input and the remaining enable inputs as strobes. Inputs include clamp diodes.