74HCT4051-Q100 Datasheet | NXP Semiconductors

74HC4051-Q100; 74HCT4051-Q100 8-channel analog multiplexer/demultiplexer Rev. 2 - 8 October 2012 Product data sheet 1. General description The 74HC4051-Q100; 74HCT4051-Q100 is a high-speed Si-gate CMOS device and is pin patible with Low-power Schottky TTL (LSTTL). The device is specified in pliance with JEDEC standard no. 7A. The 74HC4051-Q100; 74HCT4051-Q100 is an 8-channel analog multiplexer/demultiplexer with three digital select inputs (S0 to S2), an active-LOW enable input (E), eight independent inputs/outputs (Y0 to Y7) and a mon input/output (Z). With E LOW, one of the eight switches is selected (low impedance ON-state) by S0 to S2. With E HIGH, all switches are in the...