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74LVC1G14 - Single Schmitt-trigger inverter

General Description

The 74LVC1G14 provides the inverting buffer function with Schmitt-trigger input.

It is capable of transforming slowly changing input signals into sharply defined, jitter-free output signals.

The input can be driven from either 3.3 V or 5 V devices.

Key Features

  • Wide supply voltage range from 1.65 V to 5.5 V.
  • High noise immunity.
  • Complies with JEDEC standard:.
  • JESD8-7 (1.65 V to 1.95 V).
  • JESD8-5 (2.3 V to 2.7 V).
  • JESD8-B/JESD36 (2.7 V to 3.6 V).
  • 24 mA output drive (VCC = 3.0 V).
  • CMOS low power consumption.
  • Latch-up performance exceeds 250 mA.
  • Direct interface with TTL levels.
  • Unlimited rise and fall times.
  • Input accepts voltages up to 5 V.
  • Multiple package options.
  • ESD protection:.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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74LVC1G14 Single Schmitt-trigger inverter Rev. 13 — 15 March 2016 Product data sheet 1. General description The 74LVC1G14 provides the inverting buffer function with Schmitt-trigger input. It is capable of transforming slowly changing input signals into sharply defined, jitter-free output signals. The input can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment. Schmitt-trigger action at the input makes the circuit tolerant for slower input rise and fall time. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. 2.