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74LVC573A Datasheet Octal D-type Transparent Latch

Manufacturer: NXP Semiconductors

Overview: 74LVC573A Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state Rev. 5 — 19 February 2013 Product data sheet 1.

General Description

The 74LVC573A consists of eight D-type transparent latches, featuring separate D-type inputs for each latch and 3-state true outputs for bus-oriented applications.

A Latch Enable (LE) input and an Output Enable (OE) input are mon to all internal latches.

When LE is HIGH, data at the Dn inputs enters the latches.

Key Features

  • 5 V tolerant inputs/outputs, for interfacing with 5 V logic.
  • Supply voltage range from 1.2 V to 3.6 V.
  • CMOS low power consumption.
  • Direct interface with TTL levels.
  • High-impedance when VCC = 0 V.
  • Flow-through pinout architecture.
  • Complies with JEDEC standard:.
  • JESD8-7A (1.65 V to 1.95 V).
  • JESD8-5A (2.3 V to 2.7 V).
  • JESD8-C/JESD36 (2.7 V to 3.6 V).
  • ESD protection:.
  • HBM JESD22-A114F exceeds 2000 V.
  • MM JESD22-A115-B exceeds 200 V.

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74LVC573A Distributor