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74LVC573A Datasheet PDF

NXP Semiconductors 74LVC573A

The 74LVC573A consists of eight D-type transparent latches, featuring separate D-type inputs for each latch and 3-state true outputs for bus-oriented applications. When LE is HIGH, data at the Dn inputs enters the latches. When LE is LOW, the latches store the information that was present at the D-inputs one set-up time preceding the HIGH-to-LOW transition of LE.
Part No. 74LVC573A
Datasheet 74LVC573A Download
Manufacturer
NXP Semiconductors
Description Octal D-type transparent latch
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74LVC573A datasheet page 1 preview

FEATURES AND BENEFITS

● 5 V tolerant inputs/outputs, for interfacing with 5 V logic
● Supply voltage range from 1.2 V to 3.6 V
● CMOS low power consumption
● Direct interface with TTL levels
● High-impedance when VCC = 0 V
● Flow-through pinout architecture
● Complies with JEDEC standard:
● JESD8-7A (1.65 V to 1.95 V)
● JESD8-5A (2.3 V to 2.7 V)
● JESD8-C/JESD36 (2.7 V to 3.6 V)
● ESD protection:
● HBM JESD22-A114F exceeds 2000 V
● MM JESD22-A115-B exceeds 200 V
● CDM JESD22-C101E exceeds 1000 V
● Specified from 40 C to +85 C and 40 C to +125 C NXP Semiconductors 74LVC573A Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name

DESCRIPTION

74LVC573AD 40 C to +125 C SO20 plastic small outline package; 20 leads; body width 7.5 mm 74LVC573ADB 40 C to +125 C SSOP20 plastic shrink small outline package; 20 leads; body width 5.3 mm 74LVC573APW 40 C to +125 C TSSOP2...
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