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74LVC573A - Octal D-type transparent latch

Datasheet Summary

Description

The 74LVC573A is an 8-bit D-type transparent latch with 3-state outputs.

Features

  • Wide supply voltage range from 1.2 to 3.6 V.
  • Overvoltage tolerant inputs to 5.5 V.
  • CMOS low power consumption.
  • Direct interface with TTL levels.
  • IOFF circuitry provides partial Power-down mode operation.
  • High-impedance when VCC = 0 V.
  • Flow-through pinout architecture.
  • Complies with JEDEC standard:.
  • JESD8-7A (1.65 V to 1.95 V).
  • JESD8-5A (2.3 V to 2.7 V).
  • JESD8-C/JESD36 (2.7 V to 3.6 V).
  • ES.

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Datasheet preview – 74LVC573A

Datasheet Details

Part number 74LVC573A
Manufacturer nexperia
File Size 269.46 KB
Description Octal D-type transparent latch
Datasheet download datasheet 74LVC573A Datasheet
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Full PDF Text Transcription

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74LVC573A Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state Rev. 8 — 27 August 2021 Product data sheet 1. General description The 74LVC573A is an 8-bit D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its corresponding D-input changes. When LE is LOW the latches store the information that was present at the inputs a set-up time preceding the HIGH-to-LOW transition of LE. A HIGH on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the latches. Inputs can be driven from either 3.3 V or 5 V devices.
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