NXP Semiconductors 74LVC74A
The 74LVC74A is a high-performance, low-voltage Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. The 74LVC74A is a dual positive edge triggered, D-type flip-flop with individual data (D) inputs, clock (CP) inputs, set (SD) and (RD) inputs; also complementary Q and Q outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input.| Part No. | 74LVC74A |
|---|---|
| Datasheet | 74LVC74A Download |
| Manufacturer |  NXP Semiconductors |
| Description | Dual D-type flip-flop |
| Buy | Stock & Price |
FEATURES
DESCRIPTION
74LVC74A● Wide supply voltage range of 1.2 V to 3.6 V
● In accordance with JEDEC standard no. 8-1A.
● Inputs accept voltages up to 5.5 V
● CMOS low power consumption
● Direct interface with TTL levels
● Output drive capability 50 W transmission lines @ 85°C Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition, for predictable operation. Schmitt-trigger action in all data inputs makes the circuit highly tolerant to slower clock rise and fall times. QUICK REFERENCE DATA GND = 0 V; Tamb = 25°C; tr = tf ≤ 2.5 ns SYMBOL PARAMETER Propagation delay nCP to nQ, nQ nSD to nQ, nQ nRD to nQ, nQ Maximum clock frequency Input capacitance Power dissipation capacitance per flip-flop Notes 1 and 2 CONDITIONS TYPICAL 3.6 3.5 3.5 250 5.0 30 UNIT tPHL/tPLH fmax CI CPD CL = 50 pF; VCC = 3.3 V ns MHz pF pF NOTES: 1. CPD is used to determine th...
