74LVC823A Datasheet | NXP Semiconductors

DESCRIPTION FEATURES - 5-volt tolerant inputs/outputs, for interfacing with 5-volt logic - Supply voltage range of 2.7V to 3.6V - plies with JEDEC standard no. 8-1A - Inputs accept voltages up to 5.5V - CMOS low power consumption - Direct interface with TTL levels - 9-bit positive edge-triggered register - Independent register and 3-State buffer operation - Flow-through pin-out architecture The 74LVC823A is a high performance, low-power, low-voltage Si-gate CMOS device and superior to most advanced CMOS patible TTL families. Inputs can be driven from either 3.3V or 5.0V devices. In 3-state operation, outputs can handle 5V. This feature allows the use of these devices as translators in a mixed 3.3V/5V environment. The 74LVC823A is a 9-bit D-type flip-flop with mon clock (CP), Clock Enable (CE), Master Reset (MR) and 3-State outputs for bus-oriented applications. The nine flip-flops will store the state of their individual D-inputs that meet the set-up and hold times requirements on the LOW-to-HIGH CP transition provided CE is LOW. When CE is HIGH the flip-flops hold their data. A LOW on MR resets all flip-flops. When OE is LOW, the contents of the nine flip-flops is available at the outputs. When OE is HIGH, the outputs go to the high impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops. QUICK REFERENCE DATA GND = 0 V; Tamb = 25°C; tr = tf ≤ 2.5 ns SYMBOL PARAMETER Propagation delay CP to Qn Propagation delay MR to Qn Maximum clock frequency Input capacitance Power dissipation capacitance per flip-flop Notes 1 and 2 CONDITIONS CL = 50 p F; VCC = 3.3 V CL = 50 p F; VCC = 3.3 V TYPICAL 5.1 5.2 150 5.0 27 UNIT ns ns MHz p F p F t PHL/t PLH fmax CI CPD NOTES: 1. CPD is used to determine the dynamic power dissipation (PD in µW) PD = CPD × VCC2 × fi )ȍ (CL × VCC2 × fo) where: fi = input frequency in MHz; CL = output load capacity in p F; fo = output frequency in MHz; VCC = supply voltage in V; ȍ (CL × VCC2 × fo) = sum of the outputs....