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74LVC823A-Q100 - 9-bit D-type flip-flop

General Description

The 74LVC823A-Q100 is a 9-bit D-type flip-flop with common clock (pin CP), clock enable (pin CE), master reset (pin MR) and 3-state outputs (pins Qn) for bus-oriented applications.

Key Features

  • Automotive product qualification in accordance with AEC-Q100 (Grade 1).
  • Specified from -40 °C to +85 °C and from -40 °C to +125 °C.
  • 5 V tolerant inputs/outputs for interfacing with 5 V logic.
  • Wide supply voltage range from 1.2 V to 3.6 V.
  • CMOS low power consumption.
  • Direct interface with TTL levels.
  • Flow-through pinout architecture.
  • 9-bit positive edge-triggered register.
  • Independent register and 3-state buffer ope.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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74LVC823A-Q100 9-bit D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state Rev. 3 — 18 June 2020 Product data sheet 1. General description The 74LVC823A-Q100 is a 9-bit D-type flip-flop with common clock (pin CP), clock enable (pin CE), master reset (pin MR) and 3-state outputs (pins Qn) for bus-oriented applications. The 9 flip-flops stores the state of their individual D-inputs that meet the set-up and hold times requirements on the LOW to HIGH CP transition, provided pin CE is LOW. When pin CE is HIGH, the flip-flops hold their data. A LOW on pin MR resets all flip-flops. When pin OE is LOW, the contents of the 9 flip-flops are available at the outputs. When pin OE is HIGH, the outputs go to the high-impedance OFF-state.