74LVC823A-Q100 Datasheet | Nexperia

description The 74LVC823A-Q100 is a 9-bit D-type flip-flop with mon clock (pin CP), clock enable (pin CE), master reset (pin MR) and 3-state outputs (pins Qn) for bus-oriented applications. The 9 flip-flops stores the state of their individual D-inputs that meet the set-up and hold times requirements on the LOW to HIGH CP transition, provided pin CE is LOW. When pin CE is HIGH, the flip-flops hold their data. A LOW on pin MR resets all flip-flops. When pin OE is LOW, the contents of the 9 flip-flops are available at the outputs. When pin OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops. Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be applied to the outputs. These features allow the use of these devices as translators in mixed 3.3 V and 5 V applications. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits - Automotive product qualification in accordance with AEC-Q100 (Grade 1) - Specified from -40 °C to +85 °C and from -40 °C to +125 °C - 5 V tolerant inputs/outputs for interfacing with 5 V logic - Wide supply voltage range from 1.2 V to 3.6 V - CMOS low power consumption - Direct interface with TTL levels - Flow-through pinout architecture - 9-bit positive edge-triggered register - Independent register and 3-state buffer operation - plies with JEDEC standard: - JESD8-7A (1.65 V to 1.95 V) - JESD8-5A (2.3 V to 2.7 V) - JESD8-C/JESD36 (2.7 V to 3.6 V) - ESD protection: - MIL-STD-883, method 3015 exceeds 2000 V - HBM JESD22-A114F exceeds 2000 V - MM JESD22-A115-A exceeds 200 V (C = 200 p F, R = 0 Ω) - DHVQFN package with Side-Wettable Flanks enabling Automatic Optical Inspection (AOI) of solder joints 3. Ordering information Table 1. Ordering information Type number Package Temperature range 74LVC823ABQ-Q100 -40 °C to...