74LVC86A Datasheet | NXP Semiconductors

INTEGRATED CIRCUITS 74LVC86A Quad 2-input exclusive OR gate Product specification Supercedes data of 1997 Aug 11 IC24 Data Handbook 1998 Apr 28 Philips Semiconductors Philips Semiconductors Product specification Quad 2-input exclusive OR gate Features - Wide supply range of 1.2V to 3.6V - plies with JEDEC standard no. 8-1A - Inputs accept voltages up to 5.5V - CMOS low power consumption - Direct interface with TTL levels - 5-volt tolerant inputs, for interfacing with 5-volt logic QUICK REFERENCE DATA GND = 0 V; Tamb = 25°C; tr = tf ≤ 2.5 ns SYMBOL t PHL t PLH CI CPD PARAMETER Propagation delay n A, n B to n Yn Input capacitance Power dissipation capacitance per gate DESCRIPTION The 74LVC86A is a high-performance, low-power, low-voltage Si-gate CMOS device that is pin and superior to most advanced CMOS patible TTL families. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 V/5 V environment. The 74LVC86A provides the 2-input EXCLUSIVE-OR function. CONDITIONS CL = 50 p F; VCC = 3.3 V VCC = 3.3 V, VI = GND to VCC TYPICAL 3.0 5.0 28 UNIT ns p F p F NOTE: 1. CPD is used to determine the dynamic power dissipation (PD in µW) PD = CPD × VCC2 × fi )Σ (CL × VCC2 × fo) where: fi = input frequency in MHz; CL = output load capacity in p F; fo = output frequency in MHz; VCC = supply voltage in V; Σ (CL × VCC2 × fo) = sum of the outputs. ORDERING INFORMATION PACKAGES 14-Pin Plastic DIL 14-Pin Plastic SO 14-Pin Plastic SSOP Type II 14-Pin Plastic TSSOP Type I TEMPERATURE RANGE - 40°C to +85°C - 40°C to +85°C - 40°C to +85°C - 40°C to +85°C OUTSIDE NORTH AMERICA 74LVC86A N 74LVC86A D 74LVC86A DB 74LVC86A PW NORTH AMERICA 74LVC86A N 74LVC86A D 74LVC86A DB 74LVC86APW DH PKG. DWG. # SOT27-1 SOT108-1 SOT337-1 SOT402-1 PIN CONFIGURATION 1A 1B 1Y 2A 2B 2Y GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC 4B 4A 4Y 3B 3A...