74VHCT02 Datasheet PDF - NXP Quad 2-input NOR gate Specs

74VHCT02 - Quad 2-input NOR gate

This page provides the datasheet information for the 74VHCT02, a member of the 74VHC02 Quad 2-input NOR gate family.

Datasheet Summary

Description

The 74VHC02; 74VHCT02 are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL).

They are speciﬁed in compliance with JEDEC standard No.

7-A.

Features

I Balanced propagation delays I All inputs have a Schmitt-trigger action I Inputs accept voltages higher than VCC I Input levels: N The 74VHC02 operates with CMOS input level N The 74VHCT02 operates with TTL input level I ESD protection: N HBM JESD22-A114E exceeds 2000 V N MM JESD22-A115-A exceeds 200 V N CDM JESD22-C101C exceeds 1000 V I Multiple package options I Speciﬁed from.
40 °C to +85 °C and from.
40 °C to +125 °C 3. Ordering information Table 1. Ordering information T.

Datasheet Details

Part number	74VHCT02
Manufacturer	NXP
File Size	74.42 KB
Description	Quad 2-input NOR gate
Datasheet	74VHCT02 Datasheet
Additional preview pages of the 74VHCT02 datasheet.

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Full PDF Text Transcription

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74VHC02; 74VHCT02 Quad 2-input NOR gate Rev. 01 — 13 August 2009 Product data sheet 1. General description The 74VHC02; 74VHCT02 are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are speciﬁed in compliance with JEDEC standard No. 7-A. The 74VHC02; 74VHCT02 provide a quad 2-input NOR function. 2. Features I Balanced propagation delays I All inputs have a Schmitt-trigger action I Inputs accept voltages higher than VCC I Input levels: N The 74VHC02 operates with CMOS input level N The 74VHCT02 operates with TTL input level I ESD protection: N HBM JESD22-A114E exceeds 2000 V N MM JESD22-A115-A exceeds 200 V N CDM JESD22-C101C exceeds 1000 V I Multiple package options I Speciﬁed from −40 °C to +85 °C and from −40 °C to +125 °C 3.

Published: Sep 28, 2015 |