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74VHCT02 - Quad 2-input NOR gate

Download the 74VHCT02 datasheet PDF. This datasheet also covers the 74VHC02 variant, as both devices belong to the same quad 2-input nor gate family and are provided as variant models within a single manufacturer datasheet.

General Description

The 74VHC02; 74VHCT02 are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL).

They are specified in compliance with JEDEC standard No.

7-A.

Key Features

  • I Balanced propagation delays I All inputs have a Schmitt-trigger action I Inputs accept voltages higher than VCC I Input levels: N The 74VHC02 operates with CMOS input level N The 74VHCT02 operates with TTL input level I ESD protection: N HBM JESD22-A114E exceeds 2000 V N MM JESD22-A115-A exceeds 200 V N CDM JESD22-C101C exceeds 1000 V I Multiple package options I Specified from.
  • 40 °C to +85 °C and from.
  • 40 °C to +125 °C 3. Ordering information Table 1. Ordering information T.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (74VHC02-NXP.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
74VHCT02 Quad 2-input NOR gate nexperia
74VHCT02-Q100 Quad 2-input NOR gate nexperia
74VHCT02A QUAD 2-INPUT NOR GATE STMicroelectronics
74VHCT00A QUAD 2-INPUT NAND GATE STMicroelectronics
74VHCT00A Quad 2-Input NAND Gate Fairchild Semiconductor

Other Datasheets by NXP Semiconductors

Part Number Description
74VHCT02-Q100 Quad 2-input NOR gate
74VHCT08 Quad 2-input AND gate
74VHCT08-Q100 Quad 2-input AND gate
74VHCT125 Quad buffer/line driver
74VHCT126 Quad buffer/line driver

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
74VHC02; 74VHCT02 Quad 2-input NOR gate Rev. 01 — 13 August 2009 Product data sheet 1. General description The 74VHC02; 74VHCT02 are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7-A. The 74VHC02; 74VHCT02 provide a quad 2-input NOR function. 2. Features I Balanced propagation delays I All inputs have a Schmitt-trigger action I Inputs accept voltages higher than VCC I Input levels: N The 74VHC02 operates with CMOS input level N The 74VHCT02 operates with TTL input level I ESD protection: N HBM JESD22-A114E exceeds 2000 V N MM JESD22-A115-A exceeds 200 V N CDM JESD22-C101C exceeds 1000 V I Multiple package options I Specified from −40 °C to +85 °C and from −40 °C to +125 °C 3.