74VHCT02 Datasheet PDF - nexperia Quad 2-input NOR gate Specs

74VHCT02 - Quad 2-input NOR gate

This page provides the datasheet information for the 74VHCT02, a member of the 74VHC02 Quad 2-input NOR gate family.

Datasheet Summary

Description

The 74VHC02; 74VHCT02 are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL).

They are specified in compliance with JEDEC standard No.

7-A.

Features

Balanced propagation delays.
All inputs have a Schmitt-trigger action.
Inputs accept voltages higher than VCC.
Input levels:.
The 74VHC02 operates with CMOS input level.
The 74VHCT02 operates with TTL input level.
ESD protection:.
HBM JESD22-A114E exceeds 2000 V.
MM JESD22-A115-A exceeds 200 V.
CDM JESD22-C101C exceeds 1000 V.
Multiple package options.
Specified from -40 °C to +85 °C and.

Datasheet Details

Part number	74VHCT02
Manufacturer	nexperia
File Size	220.83 KB
Description	Quad 2-input NOR gate
Datasheet	74VHCT02 Datasheet
Additional preview pages of the 74VHCT02 datasheet.

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Full PDF Text Transcription

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74VHC02; 74VHCT02 Quad 2-input NOR gate Rev. 2 — 15 April 2020 Product data sheet 1. General description The 74VHC02; 74VHCT02 are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7-A. The 74VHC02; 74VHCT02 provide a quad 2-input NOR function. 2.

Published: Jul 23, 2019 |