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DSP56652 Datasheet Integrated Cellular Baseband Processor

Manufacturer: NXP Semiconductors

Overview: MOTOROLA Freescale Semiconductor, Inc. SEMICONDUCTOR TECHNICAL DATA Order this document by: DSP56652/D Rev 1, 1/99 DSP56652 Advance Information INTEGRATED CELLULAR BASEBAND PROCESSOR Motorola designed the ROM-based DSP56652 to support the rigorous demands of the cellular subscriber market. The high level of on-chip integration in the DSP56652 minimizes application system design complexity and component count, resulting in very compact implementations. This integration also yields very low-power consumption and cost-effective system performance. The DSP56652 chip combines the power of MotorolaÕs 32-bit M¥CORE (TM) MicroRISC Engine (MCU) and the DSP56600 digital signal processor (DSP) core with on-chip memory, protocol timer, and custom peripherals to provide a single-chip cellular base-band processor. Figure 1 shows the basic block diagram of the DSP56652. Freescale Semiconductor, Inc... JTAG JTAG Serial Audio CODEC I/F Timer/ PWM Watch Program Edge Dog Interrupt Timer I/O External Memory RAM 512 x 32 ROM 4K x 32 M¥CORE MicroRISC Core Clocks DSP PLL MCU OnCE DSP OnCE MCU - DSP INTERFACE 1K x 16 RAM MESSAGING UNIT DSP56652 X Data RAM (7+1)K x 16 Y Data RAM 6K x 16 Program RAM 512 x 24 X Data ROM 10K x 16 Y Data ROM 10K x 16 Program ROM 48K x 24 56600 DSP Core Smart Card I/F Keypad I/F Queued SPI UART MUX Protocol Timer Serial Audio CODEC I/F Baseband CODEC I/F AA1618 Figure 1-1 DSP56652 System Block Diagram This document contains information on a new product. Specifications and information herein are subject to change without notice. Preliminary ©1998 MOTOROLA, INC. For More Information On This Product, Go to: www.freescale.com DSP56652 Freescale Semiconductor, Inc.

General Description

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Key Features

  • DSP56652 Features RISC M.
  • CORE MCU.
  • 32-bit load/store RISC architecture.
  • Fixed 16-bit instruction length.
  • 16-entry 32-bit general-purpose register file.
  • 32-bit internal address and data buses.
  • Efficient four-stage, fully interlocked execution pipeline.
  • Single-cycle execution for most instructions, two cycles for branches and memory accesses.
  • Special branch, byte, and bit manipulation instructions.
  • Support for byte, half-word, and word memory accesses.

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