DSP56652 Datasheet PDF | NXP Semiconductors

NXP Semiconductors DSP56652

the DSP56652 minimizes application system design complexity and component count, resulting in very compact implementations. This integration also yields very low-power consumption and cost-effective system performance. The DSP56652 chip combines the power of MotorolaÕs 32-bit M¥CORE (TM) MicroRISC Engine (MCU) and the DSP56600 digital signal processor (DSP) core with on-chip memory, protocol timer, and custom peripherals to provide a single-chip cellular base-band processor.

Part No.	DSP56652
Datasheet	DSP56652 Download
Manufacturer	NXP Semiconductors
Description	INTEGRATED CELLULAR BASEBAND PROCESSOR
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FEATURES

DSP56652

FEATURES

RISC M¥CORE MCU ¥ 32-bit load/store RISC architecture ¥ Fixed 16-bit instruction length ¥ 16-entry 32-bit general-purpose register file ¥ 32-bit internal address and data buses ¥ Efficient four-stage, fully interlocked execution pipeline ¥ Single-cycle execution for most instructions, two cycles for branches and memory accesses ¥ Special branch, byte, and bit manipulation instructions ¥ Support for byte, half-word, and word memory accesses ¥ Fast interrupt support via vectoring/auto-vectoring and a 16-entry dedicated alternate register file High Performance DSP56600 Core ¥ 1 ´ engine (e.g., 70 MHz = 70 MIPS) ¥ Fully pipelined 16 ´ 16-bit parallel multiplier-accumulator (MAC) ¥ Two 40-bit accumulators including extension bits ¥ 40-bit parallel barrel shifter ¥ Highly parallel instruction set with unique DSP addressing modes ¥ Position-independent code support ¥ Nested hardware DO loops ¥ Fast auto-return interrupts ¥ On-chip support for software patching and e...