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HEF4011UB - Quadruple 2-input NAND gate

General Description

The HEF4011UB is a quadruple 2-input NAND gate.

This unbuffered single stage version provides a direct implementation of the NAND function.

The output impedance and output transition time depends on the input voltage and input rise and fall times applied.

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The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC • The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF4011UB gates Quadruple 2-input NAND gate Product specification File under Integrated Circuits, IC04 January 1995 Philips Semiconductors Product specification Quadruple 2-input NAND gate DESCRIPTION The HEF4011UB is a quadruple 2-input NAND gate. This unbuffered single stage version provides a direct implementation of the NAND function. The output impedance and output transition time depends on the input voltage and input rise and fall times applied. HEF4011UB gates Fig.2 Pinning diagram. HEF4011UBP(N): Fig.1 Functional diagram.