Description
2.2.1 Power Supplies 2.2.2 Reset 2.2.3 32MHz Oscillator 2.2.4 Radio 2.2.5 Analogue Peripherals 2.2.6 Digital Input/Output
3 CPU
4 Memory Organisation
4.1 ROM 4.2 RAM 4.3 OTP eFuse Memory 4.4 External Memory 4.4.1 External Memory Encryption 4.5 Peripherals 4.6 Internal Non-Volatile Memory (NVM) 4.7
Features
- an enhanced 32-bit RISC processor offering high coding efficiency through variable width instructions, a multi-stage instruction pipeline and low power operation with programmable clock speeds. It also includes a 2.4GHz IEEE802.15.4 compliant transceiver, 128KB of ROM, 32KB of RAM, and a comprehensive mix of analogue and digital peripherals. The JenNet-IP network stack is embedded in the device ROM. The operating current is below 18mA, allowing operation direct from a coin cell. The peripherals.
JN5142-J01 Datasheet
