MPC5607B Overview
. . . . . . . . . . . . . . . . . . . . . . . . . . .
MPC5607B Key Features
- Single issue, 32-bit CPU core plex (e200z0h)
- pliant with the Power Architecture® technology embedded category
- Enhanced instruction set allowing variable length encoding (VLE) for code size footprint reduction. With the optional en
- Up to 1.5 MB on-chip code flash memory supported with the flash memory controller
- 64 (4 × 16) KB on-chip data flash memory with ECC
- Up to 96 KB on-chip SRAM
- Memory protection unit (MPU) with 8 region descriptors
- Interrupt controller (INTC) capable of handling 204 selectable-priority interrupt sources
- Frequency modulated phase-locked loop (FMPLL)
- Crossbar switch architecture for concurrent access to peripherals, Flash, or RAM from multiple bus masters
