MPC5748G Description
NXP Semiconductors Data Sheet: Technical Data Document Number MPC5748G Rev. 6, 11/2018 MPC5748G Microcontroller Data Sheet.
MPC5748G Key Features
- 2 x 160 MHz Power Architecture® e200Z4 Dual issue, 32-bit CPU
- Single precision floating point operations
- 8 KB instruction cache and 4 KB data cache
- Variable length encoding (VLE) for significant code density improvements
- 1 x 80 MHz Power Architecture® e200Z2 Single issue, 32-bit CPU
- Using variable length encoding (VLE) for significant code size footprint reduction
- End to end ECC
- All bus masters, for example, cores generate single error correction, double error detection (SECDED) code for every bus
- SECDED covers 64-bit data and 29-bit address
- Memory interfaces