NPIC6C595 Datasheet | NXP Semiconductors

Power logic 8-bit shift register; open-drain outputs Rev. 1 - 20 August 2012 Product data sheet 1. General description The NPIC6C595 is an 8-bit serial-in/serial or parallel-out shift register with a storage register and open-drain outputs. Both the shift and storage register have separate clocks. The device Features a serial input (DS) and a serial output (Q7S) to enable cascading and an asynchronous reset input (MR). A LOW on MR resets both the shift register and storage register. Data is shifted on the LOW-to-HIGH transitions of the SHCP input. The data in the shift register is transferred to the storage register on a LOW-to-HIGH transition of the STCP input and to the Q7S...