NXP Semiconductors PCD5003
The PCD5003 is a very low power POCSAG decoder and pager controller. It supports data rates of 512, 1200 and 2400 bits/s using a single 76.8 kHz crystal. The PCD5003 is fast I2C-bus compatible (maximum 400 kbits/FEATURES
2 3 4 5 6 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 7.14 7.15 7.16 7.17 7.18 7.19 7.20 7.21 7.22 7.23 7.24 7.25 7.26 7.27 7.28 7.29 7.30 7.31 7.32 7.33 7.34 7.35 7.36 7.37 7.38 7.39 7.40 7.41 7.42APPLICATIONS
GENERAL DESCRIPTION
ORDERING INFORMATION BLOCK DIAGRAM PINNING FUNCTIONALDESCRIPTION
Introduction The POCSAG paging code Error correction Operating states ON status OFF status Reset Bit rates Oscillator Input data processing Battery saving Synchronization strategy Call termination Call data output format Sync word indication Error type indication Data transfer Receiver and oscillator control External receiver control and monitoring Battery condition input Synthesizer control Serial microcontroller interface Decoder I2C-bus access External interrupt Status/Control register Pending interrupts Out-of-Range Indication Real time clock Periodic interrupt Received call delay Alert generation Alert cadence register (03H; write) Acoustic alert Vibrator alert LED...