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PCK2509SL - 50-150 MHz 1:9 SDRAM clock driver

General Description

The PCK2509SL is a high-performance, low-skew, low-jitter, phase-locked loop (PLL) clock driver.

It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal.

It is specifically designed for use with synchronous DRAMs.

Key Features

  • Phase-Locked Loop Clock distribution for PC100/PC133 SDRAM.

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Other Datasheets by NXP Semiconductors

Part Number Description
PCK2509S 50-150 MHz 1:9 SDRAM clock driver
PCK2509SA 50-150 MHz 1:9 SDRAM clock driver
PCK2510S 50-150 MHz 1:10 SDRAM clock driver
PCK2510SA 50-150 MHz 1:10 SDRAM clock driver
PCK2510SL 50-150 MHz 1:10 SDRAM clock driver

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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INTEGRATED CIRCUITS PCK2509SL 50–150 MHz 1:9 SDRAM clock driver Product specification ICL03 — PC Motherboard ICs; Logic Products Group 2000 Dec 01 Philips Semiconductors Philips Semiconductors Product specification 50–150 MHz 1:9 SDRAM clock driver PCK2509SL FEATURES • Phase-Locked Loop Clock distribution for PC100/PC133 SDRAM applications • When outputs are disabled, the PLL and feedback output are adjusted to 50 percent, independent of the duty cycle at CLK. Each bank of outputs can be enabled or disabled separately via the control (1G and 2G) inputs. When the G inputs are high, the outputs switch in phase and frequency with CLK; when the G inputs are low, the outputs are disabled to the logic–low state.