Download PCK857 Datasheet PDF
PCK857 page 2
Page 2
PCK857 page 3
Page 3

PCK857 Description

Zero delay buffer to distribute an SSTL differential clock input pair to 10 SSTL_2 differential output pairs. Outputs are slope controlled. External feedback pin for synchronization of the outputs to the input.

PCK857 Key Features

  • Optimized for clock distribution in DDR (Double Data Rate)