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PCK857 - 66-150MHz Phase Locked Loop Differential 1:10 SDRAM Clock Driver

General Description

Zero delay buffer to distribute an SSTL differential clock input pair to 10 SSTL_2 differential output pairs.

Outputs are slope controlled.

External feedback pin for synchronization of the outputs to the input.

Key Features

  • Optimized for clock distribution in DDR (Double Data Rate) SDRAM.

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Datasheet Details

Part number PCK857
Manufacturer NXP Semiconductors
File Size 62.59 KB
Description 66-150MHz Phase Locked Loop Differential 1:10 SDRAM Clock Driver
Datasheet download datasheet PCK857 Datasheet

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Other Datasheets by NXP Semiconductors

Part Number Description
PCK111 Low voltage 1:10 differential PECL clock driver
PCK12429 25-400 MHz differential PECL clock generator
PCK2000 CK97 66/100MHz System Clock Generator
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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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INTEGRATED CIRCUITS PCK857 66–150MHz Phase Locked Loop Differential 1:10 SDRAM Clock Driver Preliminary specification 1998 Dec 10 Philips Semiconductors Philips Semiconductors Preliminary specification 66–150MHz Phase Locked Loop Differential 1:10 SDRAM Clock Driver PCK857 FEATURES • Optimized for clock distribution in DDR (Double Data Rate) SDRAM applications PIN CONFIGURATION GND 1 Y0 2 Y0 3 VDDQ 4 Y1 5 Y1 6 GND 7 GND 8 Y2 9 Y2 10 VDDQ 11 VDDQ 12 CLK 13 CLK 14 VDDQ 15 AVCC 16 AGND 17 GND 18 Y3 19 Y3 20 VDDQ 21 Y4 22 Y4 23 GND 24 48 GND 47 Y5 46 Y5 45 VDDQ 44 Y6 43 Y6 42 GND 41 GND 40 Y7 39 Y7 38 VDDQ 37 G 36 FBIN 35 FBIN 34 VDDQ 33 FBOUT 32 FBOUT 31 GND 30 Y8 29 Y8 28 VDDQ 27 Y9 26 Y9 25 GND • 1-to-10 differential clock distribution • Very low skew (< 100ps) and jitter (< 100ps