PDI1284P11 Datasheet | NXP Semiconductors

INTEGRATED CIRCUITS PDI1284P11 3.3V Parallel interface transceiver/buffer Product specification Supersedes data of 1997 Sep 15 1999 Sep 17 Philips Semiconductors Philips Semiconductors Product specification 3.3V Parallel interface transceiver/buffer Features - Asynchronous operation - 8-Bit transceivers - 6 additional buffer/driver lines peripheral to cable - 5 additional control lines from cable - 5V tolerant - ESD protection exceeds 2000V per MIL STD 883 Method 3015 and 200V per Machine Model DESCRIPTION The PDI1284P11 parallel interface chip is designed to provide an asynchronous, 8-bit, bi-directional, parallel interface for personal puters. The part includes all 19 signal lines defined by the IEEE1284 interface specification for Byte, Nibble, EPP, and ECP modes. The part is designed for hosts or peripherals operating at 3.3V to interface 3.3V or 5.0V devices. The 8 transceiver pairs (A/B 1-8) allow data transmission from the A bus to the B bus, or from the B bus to the A bus, depending on the state of the direction pin DIR. The B bus and the Y9-Y13 lines have either totem pole or resistor pull up outputs, depending on the state of the high drive enable pin HD. The A bus has only totem pole style outputs. All inputs are TTL patible with at least 400m V of input hysteresis at VCC = 3.3V. - Latch up protection exceeds 500 m A per JEDEC Std 19 - Input Hysteresis - Low Noise Operation - IEEE 1284 pliant Level 1 & 2 - Overvoltage Protection on B/Y side for OFF-state - A side 3-State option - B side active or resistive pull up option - Cable side VCC for 5V or 3V operation QUICK REFERENCE DATA SYMBOL RD RPU SR ICC VHYS t PLH/t PHL A - B/Y PARAMETER B/Y Side output resistance B/Y side pull up resistance B/Y Side slew rate Total static current Input hysteresis Propagation delay to the B/Y side outputs CONDITIONS Tamb = 25°C; GND = 0V VCC = 3.3V; VO = 1.65V ±0.2V (See Figure 2) VCC = 3.3V; Outputs, resistive pull up RL = 62Ω; CL = 50p F (See...