PDI1284P11 Datasheet | Nexperia

3.3 V parallel interface transceiver/buffer Rev. 03 - 25 August 2008 Product data sheet 1. General description The PDI1284P11 parallel interface chip is designed to provide an asynchronous, 8-bit, bidirectional, parallel interface for personal puters. The PDI1284P11 includes all 19 signal lines defined by the IEEE 1284 interface specification for Byte, Nibble, EPP, and ECP modes. The PDI1284P11 is designed for hosts or peripherals operating at 3.3 V to interface 3.3 V or 5.0 V devices. The eight transceiver pairs (A/B 1 to 8) allow data transmission from the A-bus to the B-bus, or from the B-bus to the A-bus, depending on the state of the direction pin DIR. The B-bus and the Y9 to Y13 lines have either totem pole or resistor pull-up outputs, depending on the state of the high drive enable pin HD. The A-bus has only totem pole style outputs. All inputs are TTL patible with at least 400 m V of input hysteresis at VCC = 3.3 V. 2. Features I Asynchronous operation I 8-bit transceivers I Six additional buffer/driver lines peripheral to cable I Five additional control lines from cable I 5 V tolerant I ESD protection: N HBM JESD22-A114E exceeds 2000 V N MM JESD22-A115-A exceeds 200 V I Latch-up current protection exceeds 500 m A per JEDEC Std 19 I Input hysteresis I Low-noise operation I IEEE 1284 pliant level 1 and 2 I Overvoltage protection on B/Y side for off-state I A side 3-state option I B side active or resistive pull-up option I Cable side supply voltage for 5 V or 3 V operation Nexperia 3.3 V parallel interface transceiver/buffer 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name PDI1284P11DL 0 °C to 70 °C SSOP48 PDI1284P11DGG 0 °C to 70 °C TSSOP48 Description plastic shrink small outline package; 48 leads; body width 7.5 mm plastic thin shrink small outline package; 48 leads; body width 6.1 mm Version SOT370-1 SOT362-1 PDI1284P11_3 Product data sheet Rev. 03 - 25 August...