PHB18NQ10T Datasheet | NXP Semiconductors

FEATURES - ’Trench’ technology - Low on-state resistance - Fast switching - Low thermal resistance SYMBOL VDSS = 100 V ID = 18 A g RDS(ON) ≤ 90 mΩ s GENERAL DESCRIPTION N-channel enhancement mode field-effect power transistor in a plastic envelope using ’trench’ technology. Applications:- d.c. to d.c. converters - switched mode power supplies The PHP18NQ10T is supplied in the SOT78 (TO220AB) conventional leaded package. The PHB18NQ10T is supplied in the SOT404 (D2PAK) surface mounting package. The PHD18NQ10T is supplied in the SOT428 (DPAK) surface mounting package. PINNING PIN 1 2 3 tab DESCRIPTION gate drain 1 source SOT78 (TO220AB) tab SOT404 (D2PAK) tab SOT428 (DPAK) tab 1 23 3 drain LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER VDSS VDGR VGS ID IDM PD Tj, Tstg Drain-source voltage Drain-gate voltage Gate-source voltage Continuous drain current Pulsed drain current Total power dissipation Operating junction and storage temperature CONDITIONS Tj = 25 ˚C to 175˚C Tj = 25 ˚C to 175˚C; RGS = 20 kΩ Tmb = 25 ˚C; VGS = 10 V Tmb = 100 ˚C; VGS = 10 V Tmb = 25 ˚C Tmb = 25 ˚C MIN. - 55 MAX. 100 100 ± 20 18 13 72 79 175 UNIT V V V A A A W ˚C 1 It is not possible to make connection to pin:2 of the SOT404 or SOT428 packages. August 1999 1 Rev 1.000 Philips Semiconductors Product specification N-channel Trench MOS™ transistor PHP18NQ10T, PHB18NQ10T PHD18NQ10T AVALANCHE ENERGY LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER EAS Non-repetitive avalanche energy Peak non-repetitive avalanche current CONDITIONS Unclamped inductive load, IAS = 11 A; tp = 100 µs; Tj prior to avalanche = 25˚C; VDD ≤ 25 V; RGS = 50 Ω; VGS = 10 V; refer to fig:15 MIN. MAX. 70 UNIT m J - 18 THERMAL RESISTANCES SYMBOL PARAMETER Rth j-mb Rth j-a Thermal resistance junction to mounting base Thermal resistance junction to ambient CONDITIONS MIN. SOT78...