PHP36N03LT Datasheet | NXP Semiconductors

description Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using Trench MOS technology. 1.2 Features I Logic level patible I Low gate charge 1.3 Applications I DC-to-DC converters I Switched-mode power supplies 1.4 Quick reference data I VDS ≤ 30 V I RDSon ≤ 17 mΩ I ID ≤ 43.4 A I Ptot ≤ 57.6 W 2. Pinning information Table 1. Pin 1 2 3 mb Pinning Description gate (G) drain (D) source (S) mounting base; connected to drain [1] Simplified outline mb mb Symbol 2 1 3 1 2 3 mbb076 SOT428 (DPAK) [1] SOT78 (3-lead TO-220AB) It is not possible to make a connection to pin 2 of the SOT428 package. Philips Semiconductors PHD/PHP36N03LT N-channel Trench MOS logic level FET 3. Ordering information Table 2. Ordering information Package Name PHD36N03LT PHP36N03LT DPAK SC-46 Description plastic single-ended surface-mounted package; 3 leads (one lead cropped) plastic single-ended package; heatsink mounted; 1 mounting hole; 3-lead TO-220AB Version SOT428 SOT78 Type number 4. Limiting values Table 3. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDS VDGR VGS ID IDM Ptot Tstg Tj IS ISM drain-source voltage drain-gate voltage (DC) gate-source voltage drain current peak drain current total power dissipation storage temperature junction temperature source current peak source current Tmb = 25 °C Tmb = 25 °C; pulsed; tp ≤ 10 µs Tmb = 25 °C; VGS = 10 V; see Figure 2 and 3 Tmb = 100 °C; VGS = 10 V; see Figure 2 Tmb = 25 °C; pulsed; tp ≤ 10 µs; see Figure 3 Tmb = 25 °C; see Figure 1 Conditions 25 °C ≤ Tj ≤ 175 °C 25 °C ≤ Tj ≤ 175 °C; RGS = 20 kΩ Min - 55 - 55 Max 30 30 ±20 43.4 30.7 173.6 57.6 +175 +175 43.4 173.6 Unit V V V A A A W °C °C A A Source-drain diode PHD_PHP36N03LT_2 © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 02 - 8 June 2006 2 of 13 Philips Semiconductors PHD/PHP36N03LT N-channel Trench MOS logic level...