PLS159A Description
The PLS159A is a 3-State output, registered logic element bining AND/OR gate arrays with clocked J-K flip-flops. These J-K flip-flops are dynamically convertible to D-type via a “fold-back” inverting buffer and control gate FC.
PLS159A Key Features
- High-speed version of PLS159
- fMAX = 18MHz
- 25MHz clock rate