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PN5180A0ETC3QL - High-performance multi-protocol full NFC frontend

Download the PN5180A0ETC3QL datasheet PDF. This datasheet also covers the PN5180 variant, as both devices belong to the same high-performance multi-protocol full nfc frontend family and are provided as variant models within a single manufacturer datasheet.

General Description

of the PN5180A0ET/C3 and PN5180A0ET/C4 is described in an addendum to this document.

Additional documents supporting a design-in of the PN5180 are available from NXP, this additional design-in information is not part of this document.

Key Features

  • Transmitter current up to 250 mA.
  • Dynamic Power Control (DPC) for optimized RF performance, even under detuned antenna conditions.
  • Adaptive Waveform Control (AWC) automatically adjusts the transmitter modulation for RF compliancy.
  • Adaptive Receiver Control (ARC) automatically adjusts the receiver parameters for always reliable communication.
  • Includes NXP ISO/IEC14443-A and Innovatron ISO/IEC14443-B intellectual property licensing rights.
  • Ful.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (PN5180-NXP.pdf) that lists specifications for multiple related part numbers.

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
PN5180A0xx/C3,C4 High-performance multiprotocol full NFC frontend, supporting all NFC Forum modes Rev. 4.1 — 13 March 2023 Product data sheet 1 Introduction This document describes the functionality and electrical specification of the high-power NFC IC PN5180A0HN/ C3, PN5180A0ET/C3 with firmware versions equal or higher than FW3.A and PN5180A0HN/C4, PN5180A0ET/ C4 with firmware versions equal or higher than FW4.1. The package description of the PN5180A0ET/C3 and PN5180A0ET/C4 is described in an addendum to this document. Additional documents supporting a design-in of the PN5180 are available from NXP, this additional design-in information is not part of this document.