S32V234 Datasheet | NXP Semiconductors

NXP Semiconductors Data Sheet: Technical Data S32V234 Data Sheet Features - ARM® Cortex®-A53, 64-bit CPU - Up to 1000 MHz Quad ARM Cortex-A53 - 32 KB/32 KB I-/D- L1 Cache - NEON MPE co-processor - Dual precision FPU - 2 clusters with 2 CPUs and 256 KB L2 cache each - Memory Management Unit - GIC Interrupt Controller - ECC/parity error support for its memories - Generic timers - Fault encapsulation by hardware for redundant executed application software on multiple core cluster - ARM Cortex-M4, 32-bit CPU - Up to 133 MHz - 16 KB/16 KB I-/D- L1 Cache - 32+32 KB tightly coupled memory (TCM) - ECC/parity support for its memories - Clocks - Phase Locked Loops (PLLs) - 1 external crystal oscillator (FXOSC) - 1 FIRC oscillator - System protection and power management Features - Flexible run modes to consume low power based on application needs - Peripheral clock enable register can disable clocks to unused modules, thereby reducing currents - Power gating of unused A53 cores and GPU - Low and high voltage warning and detect - Hardware CRC module to support fast cyclic redundancy checks (CRC) - 120-bit unique chip...