SAA7129H Datasheet | NXP Semiconductors

SAA7128H; SAA7129H Digital video encoder Rev. 03 - 9 December 2004 Product data sheet 1. General description The SAA7128H; SAA7129H encodes digital CR-Y-CB video data to an NTSC, PAL or SECAM CVBS or S-video signal. Simultaneously, RGB or bypassed but interpolated CR-Y-CB signals are available via three additional DACs. The circuit at a 54 MHz multiplexed digital D1 input port accepts two ITU-R BT.656 patible CR-Y-CB data streams with 720 active pixels per line in 4 : 2 : 2 multiplexed formats, for example MPEG decoded data with overlay and MPEG decoded data without overlay, where one data stream is latched at the rising clock edge and the other at the falling clock edge. It includes a sync/clock generator and on-chip DACs. 2. Features s Monolithic CMOS 3.3 V device, 5 V I2C-bus optional s Digital PAL/NTSC/SECAM encoder s System pixel frequency 13.5 MHz s 54 MHz double-speed multiplexed D1 interface capable of splitting data into two separate channels (encoded and baseband) s Three Digital-to-Analog Converters (DACs) for CVBS (CSYNC), VBS (CVBS) and C (CVBS) two times oversampled with 10-bit resolution (signals in brackets optional) s Three DACs for RED (CR), GREEN (Y) and BLUE (CB) two times oversampled with 9-bit resolution (signals in brackets optional) s An advanced posite sync is available on the CVBS output for RGB display centering s Real-time control of subcarrier s Cross-color reduction filter s Closed captioning encoding and World Standard Teletext (WST) and North-American Broadcast Text System (NABTS) teletext encoding including sequencer and filter s Copy Generation Management System (CGMS) encoding (CGMS described by standard CPR-1204 of EIAJ); 20 bits in lines 20/283 (NTSC) can be loaded via I2C-bus s Fast I2C-bus control port (400 k Hz) s Line 23 Wide Screen Signalling (WSS) encoding s Video Programming System (VPS) data encoding in line 16 (50/625 lines counting) s Encoder can be master or slave s Programmable horizontal and vertical input...