SAA7221 Description
INTEGRATED CIRCUITS DATA SHEET SAA7215; SAA7221 Integrated MPEG AVGD decoders Preliminary specification Supersedes data of 1998 Sep 11 File under Integrated Circuits, IC02 2000 Jan 31 Philips Semiconductors Preliminary specification Integrated MPEG AVGD decoders.
SAA7221 Key Features
- Integrated MPEG AVGD decoder: audio, video and graphics decoding and digital video encoding
- 5 planes display chain: background colour, background plane, MPEG display plane, graphics plane and cursor plane
- 16-Mbit or 32-Mbit external Synchronous DRAM (SDRAM) for MPEG audio and video decoding and graphics data storage
- All basic operations of the AVGD decoder are possible in both 16- and 32-Mbit configuration; enhanced performance is ach
- Targeted to BSkyB 3.0 and Canal+ basic box and web box specifications
- Fast 16-bit data + 22-bit address synchronous or asynchronous interface with external controller at up to 40.5 MHz
- Dedicated input for pressed audio and video in Packetized Elementary Stream (PES) or Elementary Stream (ES) in byte wide
- Audio and/or video can also be input via the CPU interface in PES or ES in 8 or 16-bit parallel format
- Single 27 or 40.5 MHz external clock for time base reference and internal processing. Internal system time base at 90 kH
- Flexible memory allocation under control of the external CPU enables optimized partitioning of memory for different task