SAA7201 Overview
INTEGRATED CIRCUITS DATA SHEET SAA7201 Integrated MPEG2 AVG decoder Objective specification File under Integrated Circuits, IC02 1997 Jan 29 Philips Semiconductors Objective specification Integrated MPEG2 AVG decoder.
SAA7201 Key Features
- Uses single external Synchronous DRAM (SDRAM) organized as 1M × 16 interfacing at 81 MHz; patible with the SDRAM ‘lite’
- Fast external CPU interface; 16-bit data + 8-bit address
- Dedicated input for audio and video data in PES or ES format; data input rate: ≤9 Mbytes/s in byte mode; ≤20 Mbit/s in b
- Single 27 MHz external clock for time base reference and internal processing; all required decoding and presentation clo
- Internal system time base at 90 kHz can be synchronized via CPU port
- Flexible memory allocation under control of the external CPU enables optimized partitioning of memory for different task
- Boundary scan (JTAG) plus external SDRAM self test implemented
- Supply voltage 3.3 V
- Package 160 QFP. CPU relation
- 16-bit data, 8-bit address, or 16-bit multiplexed bus; Motorola and Intel mode supported