SAA7212 Datasheet | NXP Semiconductors

INTEGRATED CIRCUITS DATA SHEET SAA7212 Integrated MPEG AVG decoder Preliminary specification Supersedes data of 1998 Feb 18 File under Integrated Circuits, IC02 1998 Sep 07 Philips Semiconductors Preliminary specification Integrated MPEG AVG decoder Features General Features - Single external Synchronous DRAM organized as 1 M × 16 interfacing at 81 MHz. Due to efficient memory use in MPEG decoding, more than 1 Mbit available for graphics - Fast 16-bit data + 8-bit address interface with external controller on 27 MHz. Sustained data rate to external SDRAM ≤9 Mbytes/s in bursts of 128 bytes - Dedicated input for audio and video in PES or ES in byte wide. Data input rate: ≤9 Mbytes/s in byte mode. Acpanying strobe signals distinguish between audio and video data - Dedicated pressed data input patible with the VLSI VES2020/2030 demultiplexers; video is received in byte format and audio serially - Audio and/or video can also be input via the CPU interface in PES/ES in 8 or 16-bit parallel format up to a peak data rate of 9 Mbytes/s - Single 27 MHz external clock for time base reference and internal processing. Internal system time base at 90 k Hz can be synchronized via CPU port. All required decoding and presentation clocks are generated internally - Flexible memory allocation under control of the external CPU enables optimized partitioning of memory for different tasks - Boundary scan testing implemented - External SDRAM self test - Supply voltage 3.3 V - Package QFP160. CPU related Features - 16 bits data, 8 bits address, or 16 bits multiplexed bus. Motorola 68xxx and Intel x 86 patible. - Support fast DMA transfer - Flexible bidirectional interface to external SDRAM. Minimum sustained rate is 9 Mbytes/s - Enhanced block mover allows 3 D data move in the external SDRAM. Picture move/Graphic bit maps construction can be done with minimum CPU support. MPEG2 system Features - Parsing of MPEG2 PES and MPEG1 packet streams - Double system time...