SAA7212 Overview
INTEGRATED CIRCUITS DATA SHEET SAA7212 Integrated MPEG AVG decoder Preliminary specification Supersedes data of 1998 Feb 18 File under Integrated Circuits, IC02 1998 Sep 07 Philips Semiconductors Preliminary specification Integrated MPEG AVG decoder.
SAA7212 Key Features
- Single external Synchronous DRAM organized as 1 M × 16 interfacing at 81 MHz. Due to efficient memory use in MPEG decodi
- Fast 16-bit data + 8-bit address interface with external controller on 27 MHz. Sustained data rate to external SDRAM ≤9
- Dedicated input for audio and video in PES or ES in byte wide. Data input rate: ≤9 Mbytes/s in byte mode. Acpanying stro
- Dedicated pressed data input patible with the VLSI VES2020/2030 demultiplexers; video is received in byte format and aud
- Audio and/or video can also be input via the CPU interface in PES/ES in 8 or 16-bit parallel format up to a peak data ra
- Single 27 MHz external clock for time base reference and internal processing. Internal system time base at 90 kHz can be
- Flexible memory allocation under control of the external CPU enables optimized partitioning of memory for different task
- Boundary scan testing implemented
- External SDRAM self test
- Supply voltage 3.3 V