SAA7388 Datasheet | NXP Semiconductors

INTEGRATED CIRCUITS DATA SHEET SAA7388 Error correction and host interface IC for CD-ROM (ELM) Preliminary specification File under Integrated Circuits, IC01 1996 Apr 26 Philips Semiconductors Preliminary specification Error correction and host interface IC for CD-ROM (ELM) CONTENTS 1 2 3 4 5 6 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 .10 8 9 10 11 11.1 11.2 11.3 11.4 11.5 11.6 11.7 11.8 12 13 14 15 Features GENERAL DESCRIPTION QUICK REFERENCE DATA ORDERING INFORMATION BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION CD-DSP interface and data input Error correction and EDC check Host interface Subcode channel Q-to-W buffering External buffer memory Sub-CPU registers Register Descriptions Sub-CPU interface Host registers CD-DSP Timings LIMITING VALUES THERMAL CHARACTERISTICS CHARACTERISTICS TIMING CHARACTERISTICS Q-to-W subcode interface timing External memory SRAM timing External memory DRAM timing Sub-CPU interface timing ATAPI host interface timing SANYO patibility mode host interface timing Oak patibility mode host interface timing Crystal oscillator PACKAGE OUTLINE SOLDERING DEFINITIONS LIFE SUPPORT APPLICATIONS 1996 Apr 26 Philips Semiconductors Preliminary specification Error correction and host interface IC for CD-ROM (ELM) 1 Features 2 GENERAL DESCRIPTION - CD-ROM (Mode 1) and CD-I (Mode 2 - Form 1 and Form 2) formats supported - Real-time error detection and correction in hardware - Suitable for octal speed, n = 8. - Maximum host transfer burst rate of 13.3 Mbyte/s - Corrects two errors per symbol with erasure correction - 36 kbit of on-chip error correction buffer RAM - 12-byte mand FIFO and 12-byte status FIFO - patible with the Advanced Technology Attachment (ATA) register set and the Advanced Technology Attachment Program Interface (ATAPI) mand set - Operates with popular memories. (up to 128 kbyte SRAM; 1 to 16 Mbit DRAM, different speed grades, nibble or byte wide) - Interface to Integrated Drive Electronics (IDE)...